Advanced High-K Gate Dielectric for High-Performance Short-Channel In0.7Ga0.3As Quantum Well Field Effect Transistors on Silicon Substrate for Low Power Logic Applications

This paper describes integration of an advanced composite high-K gate stack (4nm TaSiOx-2nm InP) in the In0.7Ga0.3As quantum-well field effect transistor (QWFET) on silicon substrate. The composite high-K gate stack enables both (i) thin electrical oxide thickness (tOXE) and low gate leakage (JG) and (ii) effective carrier confinement and high effective carrier velocity (Veff) in the QW channel. The LG=75nm In0.7Ga0.3As QWFET on Si with this composite high-K gate stack achieves high transconductance of 1750μS/μm and high drive current of 0.49mA/μm at VDS=0.5V. Introduction In0.7Ga0.3As QWFET is a promising transistor candidate for future high-speed low-power logic applications due to its excellent drive current performance at low voltage, and its demonstrated integration onto the silicon substrate [1]. However at present the InGaAs QWFET uses a Schottky gate with no gate dielectric and is subjected to large gate leakage (JG) with scaling of the upper InAlAs barrier thickness above the quantum well (QW) (Fig. 1). For further transistor scaling, there are significant challenges in identifying a suitable high dielectric constant (K) gate dielectric and its integration into the III-V transistor, which will need to simultaneously decrease tOXE (electrical gate oxide thickness), reduce JG, achieve good interface properties while retaining high carrier mobility in the transistor channel. In this work, we demonstrate a composite high-K TaSiOx-InP gate stack and its integration into the In0.7Ga0.3As QWFET, resulting in high-performance short-channel In0.7Ga0.3As QWFETs on silicon substrate with significantly decreased tOXE and reduced JG. Materials Growth and Characterization In order to retain the high carrier mobility of the QWFET, the high-K gate dielectric is deposited on the upper barrier of the QW stack rather than directly on the In0.7Ga0.3As QW channel. Two upper barrier materials, In0.52Al0.48As and InP, with identical lattice constants and similar K-values are evaluated for high-K gate dielectric integration. Figs. 2a-b show the gate capacitance (C) versus gate bias (VG) for Al2O3 capacitors on In0.52Al0.48As and InP respectively. Al2O3-InP capacitors exhibit lower frequency dispersion than Al2O3In0.52Al0.48As capacitors, suggesting InP is a more suitable upper barrier material for high-K integration. Further improvements can be made to the high-K-InP capacitors by replacing Al2O3 with TaSiOx which has higher K and similar frequency dispersion, as shown in Fig. 3. Fig. 4 shows a schematic of the new In0.7Ga0.3As QWFET for this work with 2nm InP upper barrier layer and a 4nm TaSiOx high-K gate dielectric, which form a composite TaSiOx-InP gate stack on top of the QW. The thickness of these layers is chosen to provide a thin tOXE while maintaining carrier confinement in the QW. Fig. 5 shows the band diagram of the In0.7Ga0.3As QW structure with 2nm InP upper barrier obtained using Schrödinger-Poisson simulation, which indicates good carrier confinement in the In0.7Ga0.3As QW layer. Figs. 6a-b show the TEM micrographs of the entire In0.7Ga0.3As QWFET stack on silicon by MBE and the active device layers with 2nm InP upper barrier, respectively. The effectiveness of the 2nm InP layer as an upper barrier is confirmed in Fig. 7 which shows QW electron mobility of 10,000 cm/Vs at 300K with no parallel conduction. Device Fabrication and Characterization The TEM in Fig. 8 shows the In0.7Ga0.3As QWFET with physical gate length (LG) of 75nm and the composite 4nm TaSiOx-2nm InP gate stack. The high-K TaSiOx dielectric was deposited using ALD, and the metal gate electrode consists of TiN/Pt/Au. Fig. 9a shows the C-VG measured on the In0.7Ga0.3As QWFET with the composite TaSiOx-InP gate stack. The composite gate stack has tOXE of 22Å determined from the measured intrinsic gate capacitance, and also good stability with minimal C-VG hysteresis. Included is C-VG of the Schottky-gate QWFET (extracted at RF due to high JG) with tInAlAs=5nm and tOXE=33Å. Fig. 9b shows JG as a function of VG for the In0.7Ga0.3As QWFET with (i) composite TaSiOx-InP gate stack versus (ii) Schottky gate. Insertion of high-K gate dielectric into the In0.7Ga0.3As QWFET decreases tOXE by 11Å while simultaneously reducing the gate leakage by a factor of >1000. Fig. 10 shows drain current (ID) versus gate voltage (VGS) of LG=180nm In0.7Ga0.3As QWFET with the composite TaSiOx-InP gate stack. The device shows both excellent subthreshold slope (SS) of 85mV/decade and drain induced 97-4244-5640-6/09/$26.00 ©2009 IEEE IEDM09-319 13.1.1 barrier lowering (DIBL) of 35mV/V at VDS 12 show the ID-VGS and the ID-VD respectively of the LG=75nm In0.7Ga0.3As Q composite gate stack. The drive cur transconductance (Gm) of this LG=75n 0.49mA/μm and 1750μS/μm (Fig. 13) respec of 0.5V. These performance values are reported for III-V QWFET with high-K gat 14 shows the measured effective electron the In0.7Ga0.3As QWFETs with composite stack is >3.5X higher than that in strained S This demonstrates that despite the insertion high-K gate stack, the intrinsic advantage QWFET over strained Si MOSFET is still 15-16 show the Gm and SS respectively as for the In0.7Ga0.3As QWFETs with comp versus those of the state-of-the-art III-V tran K gate dielectrics reported in literature [3-6] the transistors of this work have significan and higher Gm for all LG due to thinner tOXE a gate stack properties. Conclusions An advanced composite high-K gate sta 2nm InP) has been integrated in the In0.7Ga0 silicon substrate to enable both (i) thin tOXE (ii) effective carrier confinement and high channel. The LG=75nm In0.7Ga0.3As QW composite high-K gate stack achieves high G and high drive current of 0.49mA/μm at VD >3.5X improvement in Veff over strained Si same DIBL. Compared to the state-of-the-ar with high-K gate dielectrics reported in lite shows significantly improved SS and high due to thinner tOXE and better high-K gate sta